Radio frequency power amplifier and method using an amplitude control system

ABSTRACT

A radio frequency power amplifier and corresponding method is arranged and configured to drive a resonant load. The radio frequency power amplifier includes a radio frequency switching stage with an output that is coupled to a resonant circuit. The switching stage is configured to provide an output signal with amplitude modulation corresponding to amplitude modulation of an input signal when powered from a fixed voltage power supply. The amplifier further includes a feedback control system coupled to the input signal and the output signal, where the feedback control system includes a sequencer configured to provide a sequencer output that is used to drive the radio frequency switching stage. The amplifier also includes an amplitude control system coupled to the output of the radio frequency switching stage and configured to limit an amplitude of the output signal and in some embodiments a power recovery system.

RELATED APPLICATIONS

This application is a continuation in part of pending application titledRADIO FREQUENCY POWER AMPLIFIER AND CORRESPONDING METHOD, Ser. No.11/089,834 by Snelgrove et al., filed on Mar. 25, 2005, which is herebyincorporated herein in its entirety by reference. This application isrelated to co-pending application titled RADIO FREQUENCY POWER AMPLIFIERAND METHOD USING A PLURALITY OF FEEDBACK SYSTEMS, Docket number34-003P01 filed Apr. 28, 2006, which is hereby incorporated herein inits entirety by reference. This application also claims priority fromProvisional Application, Ser. No. 60/675,614, filed on Apr. 28, 2005 andProvisional Application, Ser. No. 60/675,704, filed on Apr. 28, 2005,which are also hereby incorporated herein in their entirety byreference.

FIELD OF THE INVENTION

This invention relates in general to communication equipment, and morespecifically to radio frequency power amplifiers.

BACKGROUND OF THE INVENTION

Radio-frequency power amplifiers are essential components oftransmitters found in radio communication systems, and are deployed invarious applications, such as mobile telephony, broadcast, wireless datanetworking, radiolocation and other fields. Generally, they function tomake copies of their inputs, which are signals generated by othercomponents of communication equipment, such as base transmitters, mobiledevices, or the like, where the copies or output signals are powerfulenough to propagate for appropriate distances. Two often conflictingrequirements that constrain radio frequency power amplifiers arelinearity and efficiency.

The linearity requirement or constraint on a radio frequency poweramplifier is that it reproduces the form of its input signal faithfully.Small distortions in the form of the output signal relative to the inputcan cause the radio frequency power amplifier output signal to interferewith other radio services, in violation of regulatory requirements, ormake it difficult or impossible to receive/demodulate the signalaccurately. These distortions may be caused, for example, by the factthat the characteristics of the components of which a radio frequencypower amplifier is composed (e.g. transistors) are non-ideal, e.g., varywith the electrical currents that they carry, which necessarily includethe signal being reproduced. A conventional method (“class A operation”)of getting good linearity in this situation is to add a large “bias”current to signal currents so that current variations due to the signalare small in comparison.

The efficiency requirement or constraint means that the amplifier shouldnot consume excessive power relative to its desired output power: thus,for example, an amplifier required to produce 10 Watts of output powermay typically consume 100 Watts. This is often caused by the use oflarge bias currents, as described above, to improve linearity. The power(90 Watts in the example) “wasted” in this way causes many problems. Forexample, the power dissipated is manifested as heat, which has to beremoved—often with large heat sinks and fans—before it causestemperature rises that damage the amplifier or other circuits. Whenequipment is battery-operated (e.g. in cell phones or in fixedinstallations (base transmitters) that are running on backup batteriesduring a power failure), battery size and hence weight and costincreases directly with power requirements.

Relatively efficient power amplifier circuits are known, and for radiofrequency power amplifiers one of the more efficient is known as type orclass “E”. These amplifiers attempt to operate their transistors as pureswitches, which in principle dissipate (and hence waste) no power. Theiroperation depends on synchronization between closing the “switch” deviceand the “ringing” of a resonant load circuit, such that the switch isonly driven closed at times when the voltage across it is almost zero.However, class E amplifiers pose problems. For example, since theiroutput power is effectively set by a power supply voltage, they aredifficult to amplitude-modulate and attempts to do so have resulted inboth poor efficiency and poor linearity. The inability to modulateamplitude severely limits the applicability of class E amplifiers inmost modern systems employing complex forms of modulation with varyingamplitude or amplitude inverting signals.

Another switching power amplifier is known as class “D”. This amplifierarchitecture has been used for audio-frequency applications. Class Damplifiers in theory have low power dissipation (e.g. a switch does notdissipate power). In practice, Class D amplifiers are continuallydischarging capacitance (e.g., when turned on) and this can amount tosignificant power dissipation at radio frequencies.

Sigma delta technology is a known technique that allows feedback to beused to linearize, for example, class “D” switching amplifiers foraudio-frequency use, but ordinarily this technology requires thatswitching events be synchronous to a fixed clock frequency. Typically, asigma delta loop samples the output of a loop filter at a fixed ratethat is independent of any input signal. This causes problems for classE radio frequency power amplifiers since their inputs need to besynchronized with a high frequency signal. Note that sigma delta anddelta sigma are expressions that may be used interchangeably in thisdocument.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying figures where like reference numerals refer toidentical or functionally similar elements throughout the separate viewsand which together with the detailed description below are incorporatedin and form part of the specification, serve to further illustratevarious embodiments and to explain various principles and advantages inaccordance with the present invention.

FIG. 1 depicts, in a simplified and representative form, a block diagramof a radio frequency power amplifier according to various exemplaryembodiments;

FIG. 2 depicts, in a simplified and representative form, a more detailedblock diagram of a radio frequency power amplifier according to one ormore exemplary embodiments;

FIG. 3 illustrates, in a simplified and representative form, a moredetailed block diagram of a radio frequency power amplifier includingone embodiment of a sequencer according to one or more exemplaryembodiments;

FIG. 4 depicts, in a simplified and representative form, a more detailedblock diagram of a radio frequency power amplifier similar to that ofFIG. 3 but including a mixer arrangement according to one or moreexemplary embodiments;

FIG. 5 shows a representative embodiment of a second feedback systemsuitable for use in one or more radio frequency power amplifiers inaccordance with various exemplary embodiments;

FIG. 6 depicts a representative embodiment of an amplitude limiting andpower recovery system in accordance with one or more exemplaryembodiments;

FIG. 7 depicts a representative block diagram of a generalized secondfeedback system suitable for use in one or more radio frequency poweramplifiers in accordance with various exemplary embodiments;

FIG. 8 through FIG. 19 show various representative waveforms resultingfrom an experimental simulation of a radio frequency power amplifier inaccordance with the embodiment depicted in FIG. 3;

FIG. 20 depicts, in a simplified and representative form, a blockdiagram of a loop filter suitable for use in one or more embodiments ofa radio frequency power amplifier;

FIG. 21 depicts, in a simplified and representative form, a blockdiagram of another loop filter suitable for use in one or moreembodiments of a radio frequency power amplifier;

FIG. 22 shows an exemplary state machine that represents an illustrativeembodiment of a sequencer that may be used, for example, in FIG. 1through FIG. 4;

FIG. 23 shows a further illustrative embodiment of a sequencer that maybe used, for example, in FIG. 1 through FIG. 4; and

FIG. 24 depicts a flow chart of a method of providing a radio frequencysignal with complex modulation according to one or more embodiments.

DETAILED DESCRIPTION

In overview, the present disclosure primarily concerns communicationequipment including radio frequency transmitters or amplifiers such asused in infrastructure equipment including base stations or incommunications units. Such radio frequency amplifiers for example, maybe found in cellular, two-way, and the like radio networks or systems inthe form of fixed or stationary and mobile equipment. The fixedequipment is often referred to as base stations or transmitters and themobile equipment can be referred to as communication units, devices,handsets, or mobile stations. Such systems and equipment are normallyused to support and provide services such as voice and datacommunication services to or for such communication units or usersthereof.

More particularly, various inventive concepts and principles areembodied in systems or constituent elements, communication units,transmitters and methods therein for providing or facilitating radiofrequency amplifiers or power amplifiers with significant improvementsin efficiency, linearity or signal to noise, and costs. Note that costsinclude costs associated with size and operational issues. Theimprovements are associated, for example, with power supplies and heatmanagement issues as impacted by improved efficiency. The improvementsalso are reflected in lower component or production costs since theconcepts and principles allow less expensive components, such as smallertransistors, to be used for higher power levels. The radio frequencypower amplifiers advantageously use a feedback control system employingin some embodiments a version of a delta sigma modulator as well as anamplitude limiting system and in some instances a second feedback systemthereby advantageously yielding a practical and readily producible poweramplifier provided such amplifiers are arranged and constructed inaccordance with the concepts and principles discussed and disclosedherein.

The communication systems and communication transmitters that are ofparticular interest are those that may employ some form of complexmodulation and that may provide or facilitate voice communicationservices or data or messaging including video services over local areanetworks (LANs) or wide area networks (WANs), such as conventional twoway systems and devices, various cellular phone systems including butnot limited to, CDMA (code division multiple access) and variantsthereof, GSM, GPRS (General Packet Radio System), 12.5G and 3G systemssuch as UMTS (Universal Mobile Telecommunication Service) systems, 4GOFDM (Orthogonal Frequency Division Multiplexed) systems, WiMax (IEEE802.16), ETSI HiperMAN and variants or evolutions thereof.

The inventive concepts and principles described and discussed herein maybe advantageously applied in any field where variable radio frequencypower is required or appropriate. For example, certain medical, heating,lighting, and sensing applications may find the concepts and principlesuseful.

The instant disclosure is provided to further explain in an enablingfashion the best modes of making and using various embodiments inaccordance with the present invention. The disclosure is further offeredto enhance an understanding and appreciation for the inventiveprinciples and advantages thereof, rather than to limit in any mannerthe invention. The invention is defined solely by the appended claimsincluding any amendments made during the pendency of this applicationand all equivalents of those claims as issued.

It is further understood that the use of relational terms, if any, suchas first and second, top and bottom, and the like are used solely todistinguish one from another entity or action without necessarilyrequiring or implying any actual such relationship or order between suchentities or actions.

Much of the inventive functionality and many of the inventive principlesare best implemented with or in integrated circuits (ICs) such as customICs with some ICs using high speed and relatively high powertechnologies. It is expected that one of ordinary skill, notwithstandingpossibly significant effort and many design choices motivated by, forexample, available time, current technology, and economicconsiderations, when guided by the concepts and principles disclosedherein will be readily capable of generating such ICs with minimalexperimentation. Therefore, in the interest of brevity and minimizationof any risk of obscuring the principles and concepts according to thepresent invention, further discussion of such ICs, if any, will belimited to the essentials with respect to the principles and concepts ofthe exemplary embodiments.

FIG. 1 through FIG. 4 illustrate various embodiments of radio frequencypower amplifiers that are arranged and constructed and operate in aninventive manner. The inventors refer to this type of power amplifier asa class M power amplifier. These power amplifiers provide replicationand amplification of an input signal that includes modulation, such asamplitude modulation, phase modulation or complex modulation (amplitudeand phase modulation) in a linear and efficient manner. Generally theseradio frequency power amplifiers utilize a novel arrangement of aswitching stage driving resonant circuits, an amplitude limiting orclipper system for reducing or limiting peak voltages across theswitching stage (and input to a feedback control loop) and a feedbackcontrol loop that operates to induce or control timing associated withswitching of the switching stage so as to linearly replicate an inputsignal including complex modulation as applied to a resultant load oramplifier output signal and to encourage the switching at times when onaverage the voltage across the switching stage is at a minimum.Heretofore it has not been possible to drive a radio frequency switchingstage so as to reproduce modulation with both good linearity and largedegrees of amplitude modulation or complex modulation.

These radio frequency power amplifiers can advantageously be implementedas one or more integrated circuits. For example, the switching stage andsome elements of the amplitude limiting or clipper system, e.g., diodes,can be implemented in a high power density gallium arsenide, galliumnitride, silicon based power device, or the like process. For thefeedback systems and feedback control loop or system or one or moreconstituent elements, a known high frequency submicron silicon basedprocess may be advantageous.

Referring to FIG. 1, a block diagram of a radio frequency poweramplifier according to various exemplary embodiments will be discussedand described. FIG. 1 shows a radio frequency power amplifier 100 thatis coupled to and arranged and configured to drive a resonant loadincluding resonant circuit 101. The radio frequency power amplifier 100will typically operate at frequencies from tens of Mega Hertz (MHz) tomultiple Giga Hertz (GHz) and is generally utilized to amplify an inputsignal to provide a higher power load output signal. The resonant loadas will be further described herein below is comprised of a combinationof inductive and capacitive elements (the resonant circuit) and a load(shown as R_(L) 102). R_(L) 102 may include, for example, a harmonicfilter, isolators, circulators, antenna, cable, or the like, that isdriven by the resultant output or load output signal.

The radio frequency power amplifier 100 comprises a radio frequencyswitching stage 103 with an output 105 that is coupled to the resonantcircuit 101 and configured to provide an output signal at output 105with complex modulation, e.g., amplitude modulation (AM) and/or phasemodulation (PM), corresponding to modulation of an input signal at input107 when, for example, powered from a fixed voltage power supply, V_(DD)109, via, e.g., a feed choke or inductor 111. The FIG. 1 embodiment ofthe radio frequency power amplifier 100 further comprises a feedbackcontrol system 113 that is coupled to the input (thus input signal 107)and the output 105 (thus output signal or one or more variants thereofas a feedback signal). Additionally a feedback system 123 and amplitudecontrol or clipper system 127 is included. Note that the input terminalor node and the input signal may alternatively be referred to as input107 or input signal 107. Similarly the output 105 and output signal at105 may alternatively be referred to as output 105 or output signal 105.

The feedback control system 113 is configured to provide a sequenceroutput at output 117 that is used to drive the radio frequency switchingstage 103. The sequencer output can be provided by, e.g., a sequencer115 that is included with the feedback control system 113.Advantageously, the sequencer output has at least one state, e.g., anOFF state, with a starting time or which begins at a variable time thatis determined by the feedback control system 113. The feedback system123 is coupled and responsive to the sequencer output at output 117(alternatively referred to as sequencer output 117) and provides asecond feedback signal at 125 that is coupled to the feedback controlsystem 113 in varying embodiments as further described below. Thesequencer output 117 will correspond to one or more of the outputsignal, the input signal, the second feedback signal, a combination ofthe output, input, and feedback signals, or the like as will be furtherdiscussed below.

The amplitude control system or clipper system 127 is coupled to theoutput of the radio frequency switching stage or output signal 105 andconfigured to control or limit an amplitude of the output signal, e.g.,to a constrained or maximum amplitude. Thus, the feedback signalcorresponds to the output signal as limited, e.g., with the maximum orconstrained amplitude. Furthermore, the output signal as limited isapplied to the resonant circuit or resonant load. Advantageously withthe amplitude control or limiting system 127 in this or otherembodiments described below, the maximum value of the output signal canbe significantly decreased (e.g., by a factor of 2-3 is some instances)which helps protect the radio frequency switching stage or allows use oftechnologies for the switching stage with lower breakdown voltages.Furthermore, when the maximum amplitude is limited or constrained withthe control or clipping system 127, the required dynamic range ofvarious circuits in the feedback control system 119, e.g., loop filter,can be designed with lower dynamic ranges which often results in usingless substrate area in integrated circuit embodiments and thereforelower costs. The radio frequency switching stage 103 may be implementedin various forms, however it may be particularly advantageous when theswitching stage together with the resonant circuit 101 is arranged as aradio frequency power amplifier similar to a class E configuration or aclass F configuration.

The radio frequency power amplifier 100 of FIG. 1 and specifically thefeedback control system 113 in one or more embodiments further comprisesa loop filter 119. The loop filter 119 is responsive to the input signaland the output signal or first feedback signal via the inter coupling asshown and the loop filter is configured to provide a filtered signal at121. The sequencer 115 is responsive directly or indirectly to thefiltered signal at 121. For a given embodiment of a sequencer there willnormally be a defined relationship between the operation of thesequencer and the output or filtered signal from the loop filter as wellas the second feedback signal, e.g. rising edge zero crossings of theloop filter signal, specifically input to the sequencer, trigger thesequencer. The loop filter may be, e.g., an nth order (n=1, 2, 3, . . .) band pass filter, or an nth order low pass filter depending on otherparticulars of the feedback control system.

For example, if the input signal is at or centered at a desired carrierfrequency (e.g., 900 MHz, 2.4 GHz, etc) or some other frequency, such asan intermediate frequency, that is above 0 hertz, a band pass filter maybe advantageous. Alternatively if the input signal is centered at 0hertz or a relatively low frequency, e.g. a base band frequency,relative to the carrier frequency, a low pass filter can be more useful.In the latter case or where the input signal is not centered at thecarrier frequency, a mixer arrangement can be employed to provide afirst feedback signal, e.g., input signal to the filter, where thefeedback signal corresponds to the output signal as down converted bythe mixer arrangement and provide a sequencer input corresponding to thefiltered signal, i.e., in some embodiments a combination of the inputsignal and the feedback signal, as up converted by the mixerarrangement.

It is further noted that the second feedback signal can be directlycombined with the filtered signal, or used as an additional input to theloop filter or may be used to affect or modify or otherwise change thefiltered signal and thus impact the sequencer input and thereforesequencer output. These alternatives will be described below inadditional detail with reference to, e.g., FIGS. 2-5 and 7. Without lossof generality portions of the following discussion will refer to anembodiment where the second feedback signal is combined with thefiltered signal from the loop filter with the resultant signal used asthe sequencer input. In these instances the second feedback signal iscoupled to the input to the sequencer. It should be understood that oneor more alternative embodiments use the second feedback signal 125 tootherwise affect or modify the filtered signal from the loop filter 119,i.e., the second feedback signal can be one component of the inputsignal for the filter or can be coupled directly to some portion of thefilter and thus affect the filtered signal.

Referring to FIG. 2, a more detailed block diagram of a radio frequencypower amplifier according to one or more exemplary embodiments will bediscussed and described. In FIG. 2, a radio frequency power amplifier200 comprises as part of a feedback control system, a loop filter 201with an input 203 coupled to a signal corresponding to an input signal205 and a first feedback signal 207. Note that the feedback signal 207and the terminal or node where the feedback signal is found willalternatively be referred to by reference numeral 207. In thisembodiment where the input signal has (or is centered about a frequencyequal to) the desired output carrier frequency, the loop filter 201 willnormally be a relatively high gain nth order band pass filter, with n=1,2, 3, . . . . Further included is a combiner 216 (analog adder) that iscoupled to an output terminal 208 and responsive to a filter output orfiltered output signal from the loop filter 201 and a second feedbacksignal at 214 provided by a second feedback system 212, e.g., sequencerfeedback. Further included and depicted is a sequencer 209 that isconfigured to provide a sequencer output at output 211. The sequenceroutput has at least one state, e.g., an OFF state, with a starting timethat corresponds to the output signal from the combiner 216, i.e.,filter output and second feedback signal as will be further discussedbelow.

Additionally included is a radio frequency switching stage 213 that isdriven by the sequencer output and configured to provide an outputsignal at 215. As shown in one or more embodiments the switching stageis supplied DC (direct current) power from a constant voltage sourceV_(DD) 220 via a feed choke or inductor 217. The output signal iscoupled to an amplitude limiter or clipper circuit that is configuredsimilarly to FIG. 1 to limit or constrain an amplitude of the outputsignal. The clipper circuit or system in one or more embodiments cancomprise a diode array 232 comprising one or more diodes with theanode(s) coupled to the output signal and the cathode(s) coupled to avoltage source 233, e.g., battery or other DC supply that can sinkcurrent where the voltage source has or maintains a reference voltage orclip voltage that with this arrangement corresponds to a maximumamplitude of the output signal. Ideally the maximum amplitude wouldequal the reference voltage of the voltage source, however the currentsinvolved and impedance as well as various parasitics of the diode(s)etc. and characteristic voltage drops will result in some differencebetween the reference voltage and the maximum amplitude of the outputsignal. Note that the voltage source 233, e.g., battery, may be used foror as a power recovery system as will be further discussed below.

The output signal is coupled via an attenuator 218 back to be combinedwith the input signal at summer 219. Thus, the feedback signal 207corresponds to the output signal 215 as limited or clipped. The summer219 provides the signal at 203 to the loop filter 201, i.e., the signalcoupled to the input of the loop filter can be an error signalcorresponding to an algebraic combination of the input signal and thefeedback signal. The radio frequency switching stage in one or moreembodiments is a field effect transistor (FET or JFET) but may also be abipolar transistor or the like. In some embodiments the FET or JFET isformed using known GaAs (gallium arsenide), GaN (gallium nitride), LDMOS(Laterally Diffused Metal Oxide Semiconductor) process technology asnoted earlier. It can be advantageous for various reasons (parasitics,similar breakdown voltage requirements, etc.) to form the diode array232 in the same technologies as the switching stage(s). Note that whilethe switching stage is shown as one transistor a plurality oftransistors may be used essentially in parallel to perform the switchingfunction. Note also that appropriate circuitry, such as additional gainstages will be needed, either as part of the sequencer or switchingstage in order to insure that the switching stage is properly driven.

Those of ordinary skill will recognize that if the sequencer 209provides a quantized output, i.e. a finite number of fixed levels orstates, the amplifier of FIG. 2 (or FIG. 1 and others) has anarchitecture similar to a delta sigma (alternatively sigma delta)converter. However, the operation and function of the sequencer isdistinctly different for a number reasons including for exampleasynchronous operation or quasi asynchronous operation (i.e., notsynchronized to a fixed clock) where the states of the sequencercorrespond to states of the output signal or first feedback signal,input signal, and second feedback signal or output from the loop filterand second feedback signal.

The output signal at 215 is applied to a resonant circuit 221 and viathe resonant circuit 221 to a load 223. Placed across the switchingstage 213 is a diode (catch or snub diode) 225 that is configured andoperates to clamp the output signal to a voltage that is non-negative,i.e., essentially at ground potential. Note that diode 225 may be aparasitic diode, e.g., source to substrate diode or the like for theswitch 213, or the switch itself may turn on or be turned on when thevoltage at 215 is at or below ground. The resonant circuit 221 includesa series resonant inductor capacitor pair 227 that couples the outputsignal as filtered by the series resonant pair 227 to the load 223.Across or in parallel with the load is a parallel resonant inductorcapacitor pair 229. Further included in the resonant circuit 221 is acapacitor 231 that is coupled in parallel with the switching stage 213.Those of ordinary skill will appreciate that the capacitor 231 willinclude at least a parasitic capacitance of switching stage 213 anddepending on the particular embodiment the capacitor 231 may onlyinclude this and other parasitic capacitance.

Those of ordinary skill in the field will recognize the switching stage213 (and others in other figures) together with the resonant circuit asshown and described can be arranged in or similar to a class Fconfiguration. Alternative embodiments of the switching stage and theresonant circuit can be arranged in a known class E configuration (forexample, eliminate the parallel inductor capacitor pair 229). Otherarchitectures for class F or class E exist and may also be utilized.Class E and F power amplifiers while taking advantage of the open orshort circuit zero power dissipation characteristics also recognize thatin practice the switching stage takes a finite time period to changebetween these states and if both voltage and current are non-zero duringthe time period between states, power will be dissipated. Such poweramplifier architectures attempt to avoid dissipating energy stored inthe parasitic capacitance (at least part of capacitor 231) of theswitching device or stage by insuring this energy is provided to orcomes from the resonant circuit, e.g., resonant circuit 221, rather thanbeing dissipated in the switching device 213. Thus these configurationsstrive to perform switching between states (ON/OFF) during those timeswhen the voltage of the output signal, i.e., signal across the switchingdevice, is ideally zero volts and furthermore if possible when thederivative of this voltage is also zero, i.e. switching currents willalso be zero.

In practice with class E or class F and others these conditions can onlybe approached and then only when the output signal is at or nearly at apredetermined amplitude or power level for a given V_(DD) level. Incontrast, the radio frequency amplifier disclosed herein and in relatedapplications, i.e., class M power amplifier, allows the amplitude orpower level of the output signal over a frequency band of interest(in-band) to vary, e.g., in accordance with AM modulation requirementsas reflected by modulation on an input signal, and encourages orcontrols the switching stage to switch between states at appropriatetimes which approach the ideal situation, i.e., with a voltage acrossthe switching device that is relatively low and approaching or at zeroas often as possible. For example, where, as here, the radio frequencyswitching stage is configured to drive a resonant load and controlled bythe feedback control system, the switching stage can be configured toswitch ON responsive to the sequencer output so that over a multitude ofswitch ON events an average voltage, e.g., root mean square of thevoltages, imposed on the resonant load and across the switching stage atthe switch ON event is less than ½, typically less than ¼ and often lessthan 1/10 of a maximum voltage imposed on the resonant load, e.g., inpractice a voltage approaching the specified breakdown voltageassociated with the radio frequency switching stage.

Furthermore, when amplitude modulation must be reproduced or included inthe output signal, known class E and class F configurations aretypically inefficient and exhibit poor linearity, i.e., knownarchitectures simply do not work as a linear radio frequency poweramplifier. In stark contrast, the radio frequency power amplifiers, i.e.class M radio frequency power amplifiers, as disclosed herein and inrelated applications are arranged such that the radio frequencyswitching stage as driven by the sequencer output is configured toprovide an output signal including complex modulation (AM or PM) asimposed on the input signal while, for example, powered from a constantvoltage power supply with reasonable efficiency and linearityperformance. Thus the present radio frequency switching stage as drivenby the sequencer output is configured to provide an output signal thatincludes an amplified replica of the input signal over an input signalbandwidth or relevant input signal bandwidth, where the input signalincludes at least one of amplitude modulation and phase modulation.

Referring to FIG. 3, a more detailed block diagram of a radio frequencypower amplifier 300 including one embodiment of a sequencer will bediscussed and described. The radio frequency power amplifier 300functionally includes many of the same entities as FIG. 1 or FIG. 2 andthus this description will not dwell on most of them. A more detailedembodiment of an amplitude control or limiting system (clipping system)350 is also shown and will be discussed. The radio frequency poweramplifier 300 includes a loop filter 301 (normally nth order band passfilter in this embodiment) with an input 303 coupled to a signalcorresponding to an input signal 305 and a feedback signal 307. Furtherincluded is a summer or combiner 316 and a sequencer 309 where thecombiner is responsive to a second feedback signal at 314 from afeedback system, e.g. sequencer feedback 312, and a filter output, e.g.,via output/input 308, from the loop filter 301 or loop filter outputsignal. The sequencer 309 is configured to provide a sequencer output atoutput 311, where the sequencer output has an OFF state with a startingtime that corresponds to the filter output signal and the secondfeedback signal (i.e., there is a defined relationship between thefilter output signal plus second feedback signal and operation of thesequencer and thus sequencer output). Additionally included is a radiofrequency switching stage 313 driven by the sequencer output andconfigured to provide an output signal at output 315 that is coupled viathe attenuator 318 to the summer 319. Thus, the feedback signal 307corresponds to the output signal as amplitude limited or clipped. Notethe OFF state corresponds specifically to switching stage 313 beingopened or in a high impedance state, i.e., OFF state.

The radio frequency switching stage 313 can be powered from a constantvoltage supply V_(DD) 320, e.g., 10 volts, via a feed inductor 317 andis coupled to the amplitude limiting system 350 which is arranged andconfigured to limit or constrain a peak or maximum amplitude of theoutput signal at 315. The switching stage 313 is also coupled to anddrives a resonant circuit 321 comprised of a series resonant inductorcapacitor pair 327 and capacitor 331 that operates to filter the outputsignal and drive a load 323. A catch or snub diode 325 is located asshown in parallel with the switching stage. The switching stage 313 withthe resonant circuit 321 will be recognized as a radio frequencyamplifier that can as known be arranged in or similar to a class Econfiguration with appropriate values of the inductors and capacitorsgiven a frequency of interest.

The sequencer 309 further comprises a flip flop, such as a D flip flop331 or other appropriately arranged flip flop or the like that isclocked, for example, from the combiner output at input 332. Thesequencer 309 is configured to provide the sequencer output in the OFFstate (low voltage state) when triggered by the combiner 316, i.e., theOFF state has a starting time that corresponds to the combiner output.Note in this embodiment, when the output signal at 308 from the loopfilter 301 plus the second feedback signal 314 crosses a switchingthreshold at a clock input 332 of the D flip flop, the Q output 333 goeshigh (Vcc since the D input is tied to Vcc) and the Q bar output 335goes low. When the Q bar output 335 or sequencer output at 311 goes low(OFF state), a switch 337 is opened.

The open switch 337 allows a capacitor 339 to begin charging toward Vccthrough a resistor 341. The junction of the capacitor and resistor iscoupled to a Reset input 343. When the capacitor has charged to theReset threshold of the D flip flop 331 at a time determined by the RCtime constant of resistor 341 and capacitor 339, the D flip flop will bereset and the Q bar output will go high, the switch 337 will be closedholding the Reset input at a low potential, and the sequencer will thusprovide the sequencer output at 311 in an ON state (switching stage 313is ON) after a time lapse determined by the Reset signal (in thisembodiment the RC time constant) for the D flip flop. This sequencer 309is often referred to as an edge triggered one shot. It has been foundthat a time lapse on the order of a half cycle of the radio frequencycarrier can be an appropriate time duration for the OFF state, e.g., at1000 MHz, approx 0.5 nanosecond. After the D flip flop has been reset,when the combiner output again goes high, the sequencer 309 will againprovide an output in the OFF state.

Note that when the sequencer output is in the OFF state, the switchingstage is an open circuit, i.e., stage is turned OFF, and the resonantcircuit 321 may be charging up through the feed inductor 317 or theinductor capacitor pair may be charging up capacitor 331 thus causing apositive going pulse in the output signal at 315. Conversely when thesequencer output is in the ON state, the switching stage is a shortcircuit, i.e., the switching stage is turned ON, the output signal at315 is approx zero volts, and the resonant circuit 321 may bedischarging through the switching stage. These and other relationshipsbetween waveforms in an embodiment of the radio frequency poweramplifier similar to FIG. 2 will become clearer with the discussion ofsimulation waveforms below where FIG. 8 through FIG. 19 are referenced.The specific voltages associated with ON or OFF states can be determinedby specific technologies that are being utilized for the sequencer aswell as the switching stage(s). For example, when depletion mode devicesare used for the switching stage the OFF state for the switching devicecan be approximately −2 volts while the ON state can be between 0 and0.5 volts. The sequencer and various driver stages will need to befashioned to provide the appropriate drive signal to the switchingstage(s).

For high-frequency operation, an appropriate sequencer operates in anasynchronous manner, i.e. there is no clock as in conventionalarchitectures. Note that for reasonable efficiency when reproducinginput signals it is necessary that the sequencer output produce a drivesignal for the class E/F amplifier that is compatible with itsrequirements, e.g., switching at or near zero voltage, etc. Thisnormally means that the sequencer will need to switch at or near thecarrier frequency and that the sequencer will need to vary or modulatethe timing of its switching decisions with a resolution that is fine incomparison with the period of the carrier, e.g. at ⅛ or smallerincrements of the period. This is in stark contrast to conventionalfeedback architectures, such as sigma-delta architectures, which aresynchronized to a clock that is independent from and thus whose phaserelationship to the carrier is essentially random.

Thus, the sequencer 309 (and 209, 115) should, in embodiments whereefficiency is desired, be configured to provide the sequencer outputwith a second state, e.g., ON state, that has a starting timecorresponding to, e.g., at or near to or on average at or near to, avoltage minimum for the output signal as will become more evident withthe review of the simulation waveforms below. As discussed above, thesequencer in certain embodiments is configured to provide the sequenceroutput where the OFF state has a minimum time duration (e.g., determinedby the RC time constant) and the sequencer output further has an ONstate having a variable time duration (in the described and variousembodiments the ON state once it begins will last until the output ofthe combiner 316, i.e., output of the loop filter as modified inaccordance with the second feedback signal, triggers the D flip flop).In the embodiment noted above, the sequencer is configured to providethe sequencer output with an OFF state having a predetermined timeduration, i.e., a time duration determined by the RC time constant.

Note that other embodiments may use a sequencer that is configured toprovide the sequencer output with an OFF state having a variable timeduration where the variable time duration is equal to or greater thanthe minimum time duration. For example a pulse generator 345 (optional)that is triggered by a positive going output or some predetermined statefrom the combiner or loop filter to provide a negative going pulse atthe Reset input and otherwise provide an open circuit will dischargecapacitor 339 and thus provide a variable time duration for the OFFstate. Note that the switch and RC circuit coupled to the Reset input ofthe D flip flop may be viewed as an edge triggered one shot, where aswith the addition of the pulse generator 345, this may be viewed as anedge triggered and re-triggerable one shot. Those of ordinary skill willappreciate that various circuit architectures can be utilized to performthe functions of the pulse generator.

Thus in the sequencer using the optional pulse generator 345, thesequencer can be configured to provide the sequencer output in the OFFstate when the filter output as modified by or in accordance with thesecond feedback signal 314 corresponds to a predetermined state (theclock level for the D flip flop) and to provide the sequencer output inthe ON state after a time lapse that is variable and that corresponds tothe minimum time duration starting at the last occurrence of thepredetermined state. As noted above, the sequencer is configured toprovide the sequencer output asynchronously, i.e., the sequencer isclocked by the combiner output, i.e., loop filter output as modified bythe second feedback signal or the control loop may be viewed as selfclocked. Note that the sequencer may also be viewed as clocked byvarious signals, e.g. the output signal (drain voltage) as thatultimately determines the filter output signal, for a given inputsignal.

In a further alternative embodiment, not specifically depicted, anenvelope detector monitors the input signal and when an envelope levelof around 20% of the peak envelope is detected, the envelope detector orfunctionality responsive thereto will operate a switch. The switch wouldadd an additional capacitor in parallel with capacitor 339. If theadditional capacitor had a capacitance that was, e.g., 2 times that ofcapacitor 339, the time constant would be about 3 times the initial timeconstant and this would extend the OFF state to approximately 3 timesthe original. The net result is the duty cycle of the switching stage isreduced when signal levels are low, the current in the feed inductor isreduced, and this ultimately results in reducing power consumption ofthe switching stage.

The amplitude limiting system 350 includes the diode or diode array 351coupled from the output or output signal at 315 to a capacitor 353 thatis coupled to ground and a DC to DC converter 355. The capacitor 353 isan RF capacitor that in some embodiments is several nano farads. Thevoltage across the capacitor 353 and input to the DC to DC converter 355is fixed or set or regulated to be at a voltage (clipping voltage orreference voltage) so as to clip or limit the upper voltage or amplitudeof the control signal to a desired level, e.g., 2-3 times V_(DD) 320.Thus, the voltage across the capacitor and at the cathode of the diodecorresponds to the maximum amplitude of the output signal.

The DC to DC converter can take various forms. In one embodiment the DCto DC converter is powered from V_(DD) 320 and simply operates as avoltage source and thus a current sink to maintain the voltage at thedesired or clipping level. This form of DC to DC converter is oftenreferred to as a 2 quadrant converter since the output voltage ismaintained either when sinking or supplying current. This approachresults in dissipating whatever power flows through the diode array 351and into the capacitor 353. In another embodiment described in moredetail below with reference to FIG. 6, the DC to DC converter 355 orsimilar converter is part of a power recovery system that is configuredto provide output power at 356 to the node at V_(DD) 320 oralternatively at the input of a further DC to DC converter 358 thatconverts primary DC power V_(S) to the V_(DD) voltage level. As will beappreciated by those of ordinary skill, the DC to DC converter 358normally receives DC power from a primary battery or from an AC to DCconverter that is coupled to an AC power grid.

Referring to FIG. 4, a more detailed block diagram of a radio frequencypower amplifier similar to that of FIG. 2, FIG. 3, etc but including amixer arrangement will be discussed and described. This radio frequencypower amplifier is shown with an amplitude limiting or control system orclipping system 425 as well as a power recovery system 427 that iscoupled to V_(DD) at 429 or a supply voltage at 431 where these elementsoperate similarly to the analogous entities discussed above. In FIG. 4,the radio frequency power amplifier 400 includes in addition to thesequencer 409 (similar to, e.g., sequencer 309), switching stage 313,resonant circuit 321, attenuator 318, etc., a mixer arrangement 401 anda feedback network or system 419. The sequencer 409, switching stage313, resonant circuit 321, attenuator 318, etc. operate in accordancewith previously discussed principles and concepts although they may beadjusted, etc. to accommodate the particulars associated with theembodiment of FIG. 4. The radio frequency power amplifier 400 of FIG. 4is arranged and constructed to receive an input signal 403 at a baseband frequency, such as zero hertz or another intermediate frequencythat is typically relatively low compared to the carrier frequency ofthe signal that is to be transmitted, frequency translate or up convertthe input signal to a carrier frequency and amplify the resultant upconverted signal to provide an output signal that is filtered andcoupled as a resultant signal to the load 323. The output signal will beat the carrier frequency and will include modulation corresponding tothe input signal. Note that the input signal 403 is a complex signalwith I (in phase) and Q (quadrature) components where the double linesin FIG. 4 are used to denote complex signals having I and Q components.

The mixer arrangement 401 includes linear I/Q mixers 405, 407 (e.g.,Gilbert cell arrangements) and is configured to provide the feedbacksignal 409, where the feedback signal corresponds to the output signalat 315 as frequency translated or down converted to the frequency of theinput signal by the mixer arrangement or more specifically mixer 405.Note that under appropriate circumstances mixers other than Gilbertcells can be used. The feedback signal 409 is combined with the inputsignal 403 in the summer 411 with the resultant complex signal coupledto a loop filter 413. The complex conversion is a multiple mixer complexconversion providing two outputs coupled to two inputs of the filter soas to provide image rejection without undue delay as discussed inSection 9 of a University of Toronto, Department of ElectricalEngineering Doctoral Thesis titled Intermediate Function Synthesis,authored by Snelgrove in December 1981, hereby incorporated herein. Themixer arrangement further provides a sequencer input at input 432 thatcorresponds to the filter output or output signal from the loop filter413 as frequency translated or up converted by the mixer arrangement401, specifically mixer 407 to the carrier frequency, and as modified inaccordance with the second feedback signal at 420. Note that only one ofthe complex signal components (I or Q) from mixer 407 is needed to drivethe sequencer or alternatively a combiner 421. In particular, the Q orimaginary component or alternatively the I or real component can beutilized; however the sequencer could be driven by a complex signal. Useof the complex signal may help in that, e.g., error-signal envelopinformation is readily available.

Thus the sequencer input or input signal corresponds to a combination ofthe input signal and the feedback signal as filtered and up converted.Note that the mixer arrangement may be viewed as part of the feedbackcontrol system of FIG. 1. Generally when the input signal is at baseband, i.e. centered at DC or zero frequency, the loop filter may beadvantageously implemented as a low pass filter and when the inputsignal is centered at another, e.g., intermediate, frequency the loopfilter is normally implemented as a band pass filter centered at theintermediate frequency. Since the filter is handling complex signalsboth the I and Q component will need to be filtered prior topresentation to the mixer 407. In either situation the loop filter isconfigured to filter the combination of the input signal and thefeedback signal. Using the mixer arrangement, while adding an apparentlevel of complexity, allows the loop filter to be implemented at a lowerfrequency and thus may allow for a more exacting or higher precisionloop filter to be implemented/provided at lower costs. Using frequencytranslation in the feedback control system allows the input signal to bepresented at base band and thus may eliminate the frequency translationat some other place in a typical transmitter lineup.

The mixer arrangement in addition to the mixers 405, 407 includes alocal oscillator 415 that provides a local oscillator signal at afrequency equal to the carrier plus or minus the center frequency of theinput signal. Thus if the input signal is at or centered at DC the localoscillator oscillates at the carrier frequency and otherwise at thecarrier frequency plus or minus the intermediate frequency. The localoscillator signal is coupled to both mixers, however the signal coupledto mixer 407 is time-shifted or phase delayed by the phase shifter 417.The phase shifter 417 in some embodiments delays the oscillator signalto mixer 407 by approximately one-quarter cycle (at the carrierfrequency) and forms the conjugate phase (the sign of the gain for the Qchannel in the down conversion mixer 405 is opposite to the sign for theQ channel in the up conversion mixer 407) for the oscillator signalapplied to the mixer 407 as compared to the signal applied to the mixer405.

The time shift can be selected or adjusted to compensate for time delaysin the feedback control system or loop or otherwise improve performanceresults in parameters such as signal to noise, linearity (noise plusdistortion), stability, or the like. One approach for varying the timeshift can utilize the second feedback system 419, which is responsive tothe output signal from the sequencer and provides a control signal orsecond feedback signal at an output 420 to the phase shifter 417. Thiscontrol or feedback signal can be used to provide or add to a phaseshift to the local oscillator signal driving mixer 407. Thus the phaseshift varies in accordance with the second feedback signal. This phaseshift can be in lieu of or in addition to a fixed phase shift that wasprovided by the phase shifter 417. Note that the output of mixer 407 isthe loop filter output signal as up converted or frequency translatedand as modified in accordance with the second feedback signal. Thesecond feedback signal can also be used in a further embodiment tomodify or change the output signal (frequency translated loop filteroutput signal) from mixer 407 by coupling the second feedback signal 420to combiner 421 where it is added to the output of the mixer 407 withthe combiner then providing an input signal to the sequencer 409. Thelatter approach for affecting the signal at the input to the sequenceris similar to the approaches discussed with reference to, e.g., FIG.2-3.

Thus the radio frequency power amplifier of FIG. 4 includes a feedbackcontrol system (401, 411, 413, 409) coupled to a signal corresponding toan input signal 403 and a first feedback signal 409 which is configuredto provide a sequencer output at 410. Further included is a secondfeedback system 419 that is responsive to the sequencer output andconfigured to provide a second feedback signal at 420 that is coupled tothe feedback control system, e.g., at phase shifter 417 or combiner 421;where the sequencer output has at least one state with a starting timethat is determined by the feedback control system; and a radio frequencyswitching stage 313 that is driven by the sequencer output andconfigured to provide an output signal, e.g., at 315, where the firstfeedback signal corresponds to the output signal. The radio frequencypower amplifier of FIG. 4 further comprises a mixer arrangement 401 thatis configured to provide the feedback signal, where the feedback signalfurther corresponds to the output signal as frequency translated by themixer arrangement. The mixer circuits or arrangement furthermoreprovides a sequencer input 432 that corresponds to the filter output asfrequency translated by the mixer arrangement and as modified, e.g., viathe phase shifter or via the combiner, in accordance with the secondfeedback signal. The loop filter 413 can be a low pass filter or a bandpass filter depending on the center frequency of the input signal.

Time domain simulations of the radio frequency power amplifier 400 ofFIG. 4 have been conducted using PC based circuit design and simulationsoftware. For illustrative purposes, the system that was simulatedproduced a modulated output signal nominally centered at 100 MHz andprocessed an information signal comprised of 4 sinusoids arbitrarilyspaced across a bandwidth of 1.25 MHz. The 4 sinusoid information signalis representative of the system processing an arbitrary wideband signalhaving a 6 dB peak-to-average power ratio. In addition, the switchingstage 313 was a GaAs FET having a 9 mm gate width, and V_(DD) 316 wasset to 12 volts. During the course of executing the simulations, systemperformance, i.e. signal-to-noise ratio, output load power efficiencyand absolute output load power, was optimized by changing componentvalues in an iterative manner through the application of electricalengineering principles. A signal-to-noise ratio of approximately 50 dBover a 1.25 MHz bandwidth, a power efficiency of 27% and an output loadin band signal power of 3.8 Watts was achieved by setting the respectivecomponents to the values noted below. The element values were; a feedinductor 317 of 100 nH (nano-henrys), a capacitor 331 of 100 pF(pico-farads), a series resonant inductor capacitor pair 321 of 11 nHand 250 pF, respectively, and a load 323 of 3 Ohms.

In contrast to these results, a Class A amplifier in an equivalentcomparison circuit, with the same input signal and output signal powerand linearity would achieve a power efficiency of approximately 7 to 8percent. Note that further optimization work may yield differentperformance results and component values. One of ordinary skill willrealize that more detailed models may be required and that differentperformance values may be obtained, for example, at higher frequencies.

Referring to FIG. 5 a representative radio frequency power amplifierincluding a more detailed diagram of a second feedback system inaccordance with various exemplary embodiments will be discussed anddescribed. In FIG. 5, a radio frequency power amplifier 500 is similarto and operates similar to the various other power amplifiers that havebeen described. An amplitude control and power recovery system 551 isshown coupled to an output signal at 515 where the system 551 operatessimilarly to those embodiments discussed above. The radio frequencypower amplifier comprises as part of a feedback control system, a loopfilter 501 with an input 503 coupled to a signal corresponding to aninput signal 505 and a first feedback signal 507. Note that the feedbacksignal 507 and the terminal or node where the feedback signal is foundwill alternatively be referred to by reference numeral 507. Furtherincluded is a combiner 545 (analog adder) that is coupled to an outputterminal 508 and responsive to a filter output or filtered output signalfrom the loop filter 501 and a second feedback signal at 544 provided bya second feedback system 527, e.g., sequencer feedback. Further includedand depicted is a sequencer 509 that is configured to provide asequencer output at output 511. The sequencer output has at least onestate, e.g., an OFF state, with a starting time that corresponds to theoutput signal from the combiner 545, i.e., filter output and secondfeedback signal as will be further discussed below. Additionallyincluded is a radio frequency switching stage or power stage 513 that isdriven by the sequencer output and configured to provide an outputsignal at 515. The output signal at 515 is coupled to a resonant load521 and is further coupled via an attenuator 518 back to be combinedwith the input signal at summer 519.

The second feedback system 527 as well as the feedback systems 123, 212,312, 419 of FIG. 1-FIG. 4 and can be implemented in various manners. Inthis instance the second feedback system comprises a feedback networkcoupled from the sequencer output to the sequencer input via thecombiner 545. In one embodiment, as depicted in FIG. 5 the secondfeedback system 527 comprises one or more delay stages with outputscoupled to a corresponding one or more gain stages with each of the gainstages having an output, where the second feedback signal corresponds toa combination of the signal at the output of each of the one or moregain stages. More specifically FIG. 5 shows a delay stage 531 that iscoupled to and responsive to the sequencer output 511 and operates topresent a delayed version of the sequencer output to gain stage 533.

The output of delay stage 531 in alternative embodiments can be coupledto a further delay stage 535 with the output of that delay stage 535coupled to a corresponding gain stage 537. The basic architecture ofdelay stages and gain stages can be repeated if desired as indicated bythe dotted lines 543. Generally, the one or more delay stages, i.e.,delay stage 531, 535, etc., may advantageously be implemented as atapped delay line with each tap coupled, respectively, to a differentone of the one or more gain stages, i.e., gain stage 533, 537, etc. Whenthe sequencer provides a 2 state output, i.e., with a high or ON stateand a low or OFF state, the delay stages can be implemented as a seriescoupled array of logic gates or buffers with each buffer or gate addinga characteristic delay. For example in one embodiment, a series coupledgroup of sixteen buffers has been used for the delay stage.

The output of the gain stages 533, 537, etc. are added together via oneor more adders or combiners 539, 541, etc. to provide the secondfeedback signal at 544. Note that in embodiments of the second feedbacksystem that use only one delay stage and one gain stage, e.g., delaystage 531 and gain stage 533, the output of gain stage 533 is the secondfeedback signal and this signal can be coupled directly to combiner 545.The feedback system or network 527 and others can take many forms,however normally at least one and often all of the one or more delaystages and at least one and often all of the corresponding one or moregain stages is operating asynchronously or continuously in the timedomain rather than in a clocked mode, i.e., the output is a function ofthe input for any instant in time. Other gain stages or delay stages mayoperate in a discrete time mode (i.e., output is a function of input atdiscrete times as determined by a clock). The delay stages essentiallyprovide a memory function in that a second feedback signal isrepresentative of the sequencer output at some past instant (the amountof the delay) in time.

FIG. 5 also illustrates another embodiment of a radio frequency poweramplifier that can provide appropriate performance results in somesituations. This embodiment includes a biasing system 547 that isconfigured to couple an offset signal (V_(OFFSET)) to the input of thesequencer, resulting in the sequencer output changing states inaccordance with the offset signal and the filter output signal. Thebiasing system or V_(OFFSET) can be used in lieu of or in addition tothe second feedback system. A typical value for V_(OFFSET) that has beensimulated with reasonable results in one power amplifier system is 10%of the rms voltage at the filter output 508.

Various experimental and simulation efforts have shown favorableperformance when the delay stages add a delay around one half cycle,e.g., ranging from 0.25 to 0.75 cycle at the carrier frequency, e.g., at1000 MHz—approximately 0.25 to 0.75 nano-second (ns) of delay for eachdelay stage. The gain of the gain stages are typically fractional valuesthat will vary depending, e.g., on the typical output level of the loopfilter as well as output level of the delay stages. For example, with a1 volt rms level at the output of the loop filter and a signal varyingfrom +1 volt to −1 volt at the output of the delay stages, a typicalvalue for the first gain stage 533 can be 0.1 ranging from 0.05 to 0.35,and can be either positive or negative (180 degree phase shift). Someembodiments perform well when gain stage 533 is a negative value (180degree phase shift), e.g., −0.1, and gain stage 537 is a positive value,e.g., 0.1, with alternating stages negative and positive. It can beexpected that for any particular implementation, these values will needto be experimentally optimized to account for various factors such asother loop delays within the power amplifier as well as other factors,e.g. loop filter, sequencer, the switching device and the load that theswitching device is driving.

An alternative embodiment (not specifically shown) of a second feedbacksystem suitable for use in one or more radio frequency power amplifiersin accordance with various exemplary embodiments includes one or moreparallel networks where each of the parallel networks is a seriescoupled delay stage and gain stage. Each of the delay stages is coupledto the sequencer output signal at 511 and thus each of the delay stagescouples a delayed version of the sequencer output to a correspondinggain stage. The output from the gain stage, either alone or togetherwith other gain stage outputs, is the second feedback signal at 544.This structure can be repeated as needed with the outputs from all gainstages combined via summers or combiners, etc. to provide the secondfeedback signal at 544. In view of the approaches discussed it will beevident that many forms of networks can be utilized as well as any orderbetween the gain stages and the delay stages, provided appropriate stepsare taken to insure the needed gain and delay is applied to the signalat the sequencer output.

Referring to FIG. 6, a representative embodiment of an amplitudelimiting or control (clipper) and power recovery system 600 inaccordance with one or more exemplary embodiments will be discussed anddescribed. The amplitude control or limiting system of FIG. 6 is coupledto the output signal 315, e.g., output of the radio frequency stage, andconfigured to limit an amplitude of the output signal. The amplitudecontrol or clipper system includes one or more diodes 351 coupled fromthe output signal to a load or a voltage or reference voltage across thecapacitor 353 or at an input 601 of power recovery system 355. Thus thereference voltage or load establishes or corresponds to a maximumamplitude or upper value for the amplitude of the output signal.

The diode(s) 351 or diode array and their in circuit disposal orphysical placement need to present minimal inductance from the switchingdevice drain to the diode or this inductance must be otherwise tuned outin order to insure protection for the switching device in terms ofbreakdown voltages across the device. The diode should have low selfimpedance at frequencies of interest, i.e. low inductance and low seriesresistance in order to provide effective amplitude limiting or control.The diode will need reasonably fast, relative to the radio frequency,recovery characteristics when switching from a forward to reverse biasedstate. The diode should have low parasitic capacitance and demonstratelimited change in that capacitance when switching from a forward toreverse bias conditions, although again some of this capacitance orchange in capacitance can be tuned out or otherwise compensated for withthe resonant load characteristics. The capacitor 353 needs to have goodhigh frequency characteristics (low impedance). The capacitor 353 isnormally in parallel with a much larger capacitor at the input of the DCto DC converter 603 and thus energy stored on capacitor 353 by pulses atthe radio frequency will flow to this larger capacitance.

The power recovery system 355 includes in various embodiments, DC to DCconverter 603 which is configured to provide output power, e.g., aportion of the DC power for the radio frequency switching stage or poweramplifier at V_(DD) 356 or V_(S) 358. The DC to DC converter 603 can bea known Buck regulator arranged for down conversion of the input voltageat 605 or in some embodiments a synchronized version (typical Buckregulator diode replaced with a switch and corresponding control logicto synchronize this switch with the conventional switch), with theoutput section of this regulator replaced with a current source 607 inone or more generally known configurations. Thus the DC to DC converter603 supplies an output current at 609, when enabled via enable signal at611 as provided by enabling circuitry 610.

The enabling circuitry is configured to enable the DC to DC converterwhen a comparison of the voltage at 601 and a reference voltage at 615satisfies a known condition, e.g., the voltage at 601 exceeds thereference voltage at 615, as determined by comparator 613. In practicethe reference voltage at 615 can be provided via a resistor dividercoupled to V_(DD) or any other convenient DC voltage and the voltage atthe positive input of the comparator can be provided by a resistordivider coupled to 601 where the various resistors are selected to setthe reference voltage and the voltage at the positive input of thecomparator and thus the corresponding voltage at 601 (i.e. upper valueof amplitude or maximum amplitude for the output signal).

One further aspect of the power recovery system 355 or one or moreembodiments of the DC to DC converter is the electronic switch 617. Theelectronic switch allows the power recovery system to be isolated fromthe voltages V_(DD) or V_(S) (which ever is coupled to the output) whenthe power recovery system is not supplying any power, i.e., when notenabled or if enabled until the DC to DC converter has ramped upsufficiently and current 609 is available. The electronic switch 617basically compares the voltage at the output of the DC to DC converterto the voltage V_(DD) or V_(S) and when the voltage at the output of theconverter exceeds the destination supply voltage (V_(DD) or V_(S)) theswitch is closed and the current flows to the destination. Theelectronic switch functionally is a diode, however advantageously theswitch has significantly lower voltage drop than a diode, e.g., 0.1volts versus 0.7 volts.

As power is recovered and provided to the destination supply voltage,the voltage across the capacitor 353 or input to the DC to DC converterwill begin to drop, the converter will be disabled, the electronicswitch 617 will open, and the input voltage will rise again as theoutput signal is limited or clipped. Note that some hysteresis in theoperation of the comparator 613 can be helpful in order to avoid unduehunting. Thus the power recovery system and specifically the DC to DCconverter in contrast to conventional converters is configured andoperates to regulate the voltage at the input to the DC to DC converterand converts stored energy in capacitor 353 as well as capacitance atthe input to the converter into power that is recovered.

Use of the FIG. 6 embodiment of an amplitude control or clipper systemor functionally similar systems in addition to the benefits ofprotecting the switching stage from over voltage conditions and reducingdynamic range requirements of the feedback control system provides othersignificant advantages. For example, as shown in FIG. 19 below, improvedsignal to noise or linearity has been observed in various experimentaland simulation exercises, due in part to better control over theamplitude of the output voltage and thus range of errors that need to becorrected by the feedback control system. Furthermore, given that themaximum amplitude is limited, the switching devices can be driven harderwhich often results in more output power than a typical class Eamplifier for a given switching stage breakdown voltage. This is theresult of having more pulses in the output signal that are closer tobeing a square pulse. A square pulse wave maximizes output power for agiven maximum voltage constraint. Furthermore, the power recovery systemallows the square pulses to be used without unduly compromising overallefficiency.

Referring to FIG. 7 a representative block diagram of a generalizedsecond feedback system suitable for use in one or more radio frequencypower amplifiers in accordance with various exemplary embodiments willbe discussed and described. The radio frequency power amplifier of FIG.7 comprises many of the same elements as FIG. 5 including input signal505 and a feedback control system further comprising a loop filter 701and a sequencer 509 with an output of the loop filter 508 coupled viacombiner 545 to an input of the sequencer 509. The loop filter iscoupled to a signal corresponding to the input signal and the firstfeedback signal, e.g., sum of these signals from summer 519, and thefeedback signal corresponds to the output signal 515 as reduced byattenuator 518. The output signal 515 is provided by a switching stage513 and this signal is coupled to the load 521. The sequencer drives theswitching stage.

Further shown is a second feedback system that provides one or moresecond feedback signals with one provided by feedback network 703 whichis coupled to combiner 545 and thus to the sequencer input and anotherprovided by feedback network 707 which is coupled at 709 to summer 519and thus the input to the loop filter 701 or at 711 to the loop filter701. The second feedback system 727, specifically one or more offeedback networks 703, 707 includes one or more of a discrete timeportion, a continuous time portion, and a memory portion (portion wherepresent output is affected at least in part by a previous input). Notethat only one of the feedback networks needs to be present in someembodiments, e.g., feedback network 703 in various of the abovediscussed embodiments where the feedback system is coupled to thesequencer input. In other embodiments only feedback network 707 ispresent and serves similar purposes provided appropriate responses arechosen for the network, e.g., different delays and gains. When thefeedback network is coupled to the loop filter it can be done via atransconductor coupled to an internal filter state (presuming the loopfilter is implemented using gmC elements), thus varying the output ofthe loop filter in accordance with the second feedback signal.

Referring to FIG. 8 through FIG. 19, various representative waveformscaptured from an experimental simulation of a radio frequency poweramplifier in accordance with the embodiment depicted in FIG. 2 (less theparallel network 229) will be discussed and described. Note that theinput signal in FIG. 2 is centered at the carrier frequency, i.e., afrequency of 875 MHz. FIG. 8 shows the input signal 205 over a one microsecond (1 μs) time period. Note that the input signal envelopedemonstrates that the input signal includes amplitude (AM) modulationwhere the envelope varies from approx 300 millivolts to near zero insome instances with an approximately 6 dB peak to average ratio. Notealso that the input signal includes phase modulation, i.e., PM, that isnot particularly evident. The input signal is similar to that found forexample, in code division multiple access (CDMA) systems, such aswideband CDMA systems. FIG. 9 shows the same input signal over the first200 nano seconds (200 nsec) where again the AM modulation is clearlyevident. FIG. 10 shows a 20 nsec portion of the input signal where thecarrier signal (approximately 875 MHz) is evident, as well as AM or PMmodulation. FIG. 11-FIG. 18 show the waveforms observed at variouspoints in the radio frequency amplifier for the same 20 ns time period.

FIG. 11 shows the feedback signal 207 over the 20 ns time period. Thisfeedback signal corresponds to the output signal at 215 with a delayequal to one cycle at the radio frequency carrier, i.e. at 875MHz—approximately. 1.14 ns (compare to FIG. 17). Each of the pulsesarises or occurs when the sequencer 209 enters the OFF state and theswitching stage 213 becomes an open circuit. The feed inductor 217,capacitor 231 (some or all of which may be parasitic capacitance ofswitching stage 213 or parasitic capacitance of diode array 232) andresonant circuit 221 as well as the charge states (conditions when timeOFF state starts) for each of the elements determine the particular formof the respective pulses. The pulses end when the sequencer enters theON state and the switching device becomes a short circuit. The inputsignal and the feedback signal are combined in the summer 219 and yieldthe waveform of FIG. 12. Note that the waveform of FIG. 12 isessentially the difference between the input and the feedback signals.This is the waveform that is input to the loop filter at input 203.

The loop filter is typically a bandpass filter in the FIG. 2 poweramplifier embodiment as earlier noted and as will be further describedbelow. The output of the loop filter is shown in FIG. 13. The waveformof FIG. 13 is coupled to the combiner 216 at input 208 along with thesecond feedback signal, shown in FIG. 14, from the second feedbacksystem 212. Note that the second feedback system used in thesesimulations included a single delay stage with slightly less than T/2delay (at 875 MHz approx. 0.57 ns where the delay used was approx. 0.5ns) and a single gain stage with an approximate gain setting of −0.1.These signals are added together to provide the combiner output signal,i.e., input signal for the sequencer 209 shown in FIG. 15. Thediscontinuities observed in the FIG. 15 waveform is the result of addingthe second feedback signal (essentially a two state signal ignoringnon-zero switching times) to the filter output signal.

The sequencer output signal at 211 is shown in FIG. 16. The sequenceroutput signal is a quantized signal that in this embodiment, ignoringsmall non-zero switching times, includes an OFF state (sequencer outputsignal is low at −1 volts and switching stage 213 is essentially an opencircuit or OFF) and additionally an ON state (sequencer output signal ishigh at 1 volts and switching stage is essentially a short circuit orON), with each state occurring multiple times. Note that rising edges(zero crossings) 1501 in FIG. 15 result in the sequencer entering theOFF state 1601 (three occurrences specifically labeled 1601). The OFFstate in the particular sequencer embodiment (see 309 in FIG. 3) withthe output signal shown in FIG. 16 lasts for a minimum time period ofapproximately or slightly less than T/2 1603 (i.e., a half-cycle of thecarrier frequency—at 875 MHz is approx 0.57 ns, thus use a minimum timeperiod of approx. 0.5 ns). Thus the sequencer output includes an OFFstate that begins at a variable time that corresponds to the combineroutput in FIG. 15 (filter output as modified in accordance with thesecond feedback signal) or corresponds to the output signal (see FIG. 17as further described below).

Note that rising edges, e.g., 1503, 1505, etc., at the output of thecombiner 216 (sequencer input FIG. 14) that occur while the sequencer isin the OFF state (e.g., 1605, 1607) retrigger the sequencer and resultin extending the duration of the OFF state. This is the result of usingthe optional pulse generator 345 or similar functionality (e.g.,re-triggerable one shot). The OFF state can be extended by the length oftime between the two or more (in one instance 3, i.e., 1501, 1502, 1503)successive rising edges. Similar circumstances in the sequencer inputresult in the extended OFF state 1607. If the re-triggering function wasnot used there would be no impact from a rising edge during an OFF stateor period. It is also noted that the frequency of occurrence of the OFFstate varies from one time period or frame to another as readilyobserved from FIG. 16 and also varies from the frequency of the inputsignal (see FIG. 10).

By observation and comparison of FIG. 14 and FIG. 16, it is evident thatthe amplitude of the second feedback signal in FIG. 14 results fromapplying a gain factor of approximately −0.1 to the sequencer output anda delay of approximately 0.5 ns via the second feedback system, i.e.,the amplitude of the second feedback signal is approximately 10% of theamplitude of the sequencer output and the signal has been inverted(minus sign=180 degree phase shift) and delayed by approx 0.5 ns(compare 1601 to 1401). Furthermore the second feedback signal hasresulted in the sequencer being retriggered on various occasions (seerising edge crossing zero due to discontinuity at 1502 and 1507.

Essentially the second feedback signal in FIG. 14 when added to thefilter output signal in FIG. 13 either advances or retards the time whenthe rising edge of the combiner output or sequencer input crosses zeroand thus the variable time when the sequencer enters or assumes the OFFstate. For example 1501 and 1509 shows four of many instances where thezero crossing has been delayed or retarded from when it would haveoccurred if the second feedback signal was not present. Two instances ofmany where the zero crossings have been advanced relative to when theywould have occurred without the second feedback signal are shown at1511. Thus the second feedback system and signal is provided anddeployed to cause the OFF state to begin earlier with the secondfeedback signal than without the second feedback signal in someinstances. Furthermore, the second feedback system and signal isprovided and deployed to cause the OFF state to begin later with thesecond feedback signal than without the second feedback signal invarious instances.

Additionally as observed, e.g., in the 3-6 ns and again between 11 and13 ns range, in FIG. 15, the second feedback signal has a largerrelative impact on the sequencer input signal and thus aforementionedvariable time when the filter output signal is smaller than when, e.g.,in the 15-18 ns range, the filter output signal is larger(discontinuities are larger portion of the entire sequencer input signalwhen the filter output signal is smaller). Thus the second feedbacksignal is provided and deployed to affect the variable time when thesequencer is triggered or enters an OFF state to a greater extent whenthe filtered signal is smaller than when the filtered signal is larger.

Also it will be evident that the second feedback system and signal aredeployed and operate to over steer the sequencer output in the sensethat long (using a T/2 reference length) duration ON states are longerdue to the second feedback signal and correspondingly the variable timeassociated with the beginning of an OFF state is delayed due to thesecond feedback signal than either would have been without the secondfeedback signal. Similarly the second feedback system and signal furtheroperates to over steer the sequencer output in the sense that short(using the T/2 reference length) duration ON states are shorter andcorrespondingly the variable time associated with the beginning of anOFF state is advanced due to the second feedback signal than eitherwould have been without the second feedback signal.

For example the ON state 1609 would have been longer than T/2 when azero crossing due to the rising edge at 1509 is projected without theeffects of the second feedback signal and is even longer (zero crossingdelayed) with the effects of the second feedback signal. Similarobservations can be made with reference to ON state 1611. In contrast ashort ON state 1613, 1615 is even shorter due to the zero crossing beingadvanced (see 1511, 1513) due to the second feedback signal. In essencethe second feedback signal magnifies or operates to increase adifference (magnitude) between the reference duration of the ON stateand an actual duration. This may be viewed as the second feedback signalincreasing the second moment, variance, or variation in the duration ofthe ON states as well as the variable time when the OFF state begins.

FIG. 17 shows the output signal at 215, i.e., at the drain of theswitching stage 213, that results given the sequencer output signal ofFIG. 16, etc. It will be observed that pulses, e.g., 1701, are typicallygenerated whenever the sequencer is in a corresponding OFF state, e.g.,1617, 1619 and others. Note that the amplitudes of some of the pulsesare limited to approximately 30 volts (i.e., 2.5-3 times a V_(DD)) andthis is due to the clipper or amplitude limiting or control system asdescribed and discussed above. It is further noteworthy that without thelimiting or control systems it is not uncommon to see pulses reachingamplitudes of 5 to 7 times V_(DD). Pulses end or are terminated wheneverthe sequencer starts or initiates an ON state, e.g., 1703 (see 1609),and the switching stage becomes a short circuit, although some end longbefore that (see pulse at 7 ns). When the pulses end before the ON statebegins, often either the switching stage or the snub diode will beconducting current from ground to the output at 215. The ON state isnormally initiated at a starting time that corresponds to a voltageminimum in the output signal. For example, pulses 1705 are terminatednear a voltage minimum and for these pulses as readily observed near orshortly before/after the voltage minimum. As another observation, pulses1706 and others are terminated near a voltage minimum and for thesepulses near zero volts across the switching stage. In some instances,pulses are abruptly terminated, e.g., 1707, however the majority of thepulses are terminated at or near a voltage minimum and on average near 0volts across the switching stage. When the sequencer output and thusswitching device is in an OFF state for a long time period, e.g., 1605,the output signal can include multiple pulses 1709 (indicating ringingin the resonant load). A comparison of the feedback signal in FIG. 11with the output signal in FIG. 17 shows a factor of 10 attenuation inthe amplitude of the feedback signal as well as a delay of approximatelyone cycle at the carrier frequency.

The load voltage after some filtering and thus removal of out of bandnoise and harmonic content is shown in FIG. 18. FIG. 18 shows a waveformof the voltage across the load 223 that results from the output waveformof FIG. 17 with peak amplitudes approaching 6 or so volts. This waveformincludes significant amounts of essentially switching or quantizationnoise as well as 2^(nd) and higher order harmonics that may be readilyremoved with an appropriate harmonic filter, e.g. a band pass radiofrequency filter, before applying the resultant signal to an antenna orcable or the like.

Those familiar with class F or class E power amplifiers will note thatnormally these stages are designed to and typically will switch at nearzero volts (pulses 1701) across the switching stage, thereby minimizingpower dissipation in the switching stage. However class F or class E inorder to consistently switch near zero volts have to provide near amaximum output power given the voltage supply, V_(DD), for the switchingstage and other design values, i.e. class E and class F are not normallycapable of AM modulation or PM modulation of more than very smalldeviations without degrading either efficiency or linearity andtypically both. In the embodiment simulated above, the class E amplifieris driven to replicate AM and PM modulation on the input signal, e.g.provide an output signal that is often less than the maximum outputgiven a particular voltage supply, V_(DD) 220, as well as replicate PMmodulation. One of the artifacts of reproducing AM and PM modulationusing the power amplifier of FIG. 2 is occasionally closing theswitching stage when the output signal is not near zero volts, e.g.,pulses 1707. In these instances, power will be dissipated by theswitching stage at least during the switching time when both voltage andcurrent are non-zero.

However this dissipation can be minimized by turning the switching stageON when the output signal voltage is near a minimum voltage as depictedby many of the pulses in FIG. 17 and particularly pulses such as pulses1701 and the like. Note that other 20 nsec segments of waveforms such asthose of FIG. 10 through FIG. 18 may show many of the output pulsesbeing terminated at near zero voltage or many of the output pulses beingterminated earlier/later than the minimum output voltage. If the pulsesare terminated near a minimum voltage the resultant efficiency will beclose to the best efficiency available from the class F or class E poweramplifier driven to replicate complex modulation including AM and PMmodulation using the feedback control systems variously described above.

For example, if the efficiency does not suffer more than 15% as a resultof the specific time (before or after minimum voltage) that the outputpulses are terminated (switching stage enters ON state), the startingtime of the second or ON state may be viewed as near to or correspondingto a voltage minimum for the output signal. Note also that the switchingstage when driven by the sequencer in the feedback control system mayturn the switching device ON at a point that is not close to a voltageminimum for a particular pulse in order to provide near optimum turn ontimes for many successive pulses. In essence, if on average the pulsesare being terminated near a voltage minimum, efficiency will be near anoptimum value given that AM and PM modulation is being imposed on acarrier signal by a class E or class F or the like power amplifier.

FIG. 19 shows a close in frequency spectrum of the waveform of FIG. 18which results when a second feedback system (one delay and one gainstage) and the amplitude limiting or clipping systems as discussed anddescribed above is used with the resultant spectra 1903 depicted as adarker line. This spectrum is centered at a frequency near 875 MHz andshows desired sidebands 1905 clearly indicative of AM and PM modulationcomponents as well as the undesirable quantization noise, etc. Note thatin band, the quantization noise, etc is down by more than 60 dB in the10 MHz bandwidth centered at the carrier frequency. This spectra iscompared to another spectra of a corresponding waveform where theamplitude limiting system is not utilized with this comparison spectra1901 depicted with a lighter line. By observation, significantimprovement in in-band (near carrier) noise or undesirable energycomponents 1909 for spectra 1901 as compared to 1907 for spectra 1903have been realized with the use of the amplitude control or limitingsystem. Quantitative measurements with the amplitude limiting or controlsystem showed a total signal to noise level over the 10 MHz band to beapproximately 52 dB whereas without the amplitude limiting the totalsignal to noise was 45 dB. Efficiency with the amplitude limiting systemwas approximately 23% and approximately 24% without the amplitudelimiting system with an output signal power of approximately 6 watts.These simulation results were obtained without the benefit of powerrecovery.

Generally the particular implementation of a sequencer will depend on amultitude of factors including the switching stage, feed inductor,resonant circuit(s) amplitude control or clipping system, feedbackpath(s) and loop filter gain and phase parameters. The sequencer shouldbe implemented such that given all of the other parameters the sequenceroutput is provided in the proper state and at the proper time and forthe proper time duration to cause the switching stage to turn ON or OFFso as to generate an output signal that when fed back and combined withthe input signal will drive the output of the loop filter toward zero.This may be referred to as generating a counter phase or opposing phaseloop filter output. Similarly, the particular implementation of thesecond feedback system will depend on other factors and elements in theradio frequency power amplifier and feedback control system andspecifically various delays therein. Generally the second feedbacksystem will have less inherent loop delay than the feedback controlsystem in combination with the switching stage. This fact or observationcan be used to “predict” what will occur with the switching stage andthe like and compensate for undesirable aspects thereof. For example, inthe simulations discussed above the second feedback signal resultingfrom a given sequencer output arrives at or begins to affect the inputto the sequencer at least T/2 seconds before the output signal andresultant feedback signal begins to have an impact on the sequencerinput.

Referring to FIG. 20, a block diagram of a loop filter suitable for usein one or more embodiments of a radio frequency power amplifier will bediscussed and described. The loop filter of FIG. 20 is a knowntransconductance capacitor (gm-C) filter that is shown in a generalizedform, i.e., the filter can be a low pass or band pass filter dependingon the selection for gains A1, A2 2001, 2003. For example, if A1 is setto unity (1) and A2 to zero (0) a band pass filter results. As shown thefilter has two inputs, namely the feedback signal 2005 and input signal2007 (analogous, e.g., to output signal at 105, 215, 315 and inputsignal 107, 205, 305, etc). Note that the filter of FIG. 20 is alsoacting as the summer in FIG. 2-FIG. 5, etc.

The filter of FIG. 20 when implemented as a band pass filter with thevalues of gm and C shown, A1=1, and A2=0, has a center frequency of 2GHz and a theoretically infinite Q (i.e., not limited by an impedance atthe output of the gm blocks). The roll off characteristic on either sideof the center frequency is 20 dB per decade. Note that this filter maybe frequency scaled to any value of interest (carrier frequency orintermediate frequency) according to known techniques, e.g. increasingthe capacitor values will lower the center frequency. The values of A1and A2 can be selected/adjusted to tune and optimize the systemperformance of the radio frequency power amplifier and thus account forcircuit parasitics and various other non-idealities. Generally it hasbeen found that adjusting these values can improve signal to noiseperformance with limited impact on efficiency. Various classes ofbandpass filters can be employed to realize the loop filter when a bandpass version is needed. A fourth order filter may be used in embodimentsof a radio frequency power amplifier with a non-DC centered inputsignal, where the filter has a transfer function of the form:${L(s)} = \frac{( {{{- 0.496}\quad s^{3}} - {0.0609\quad s^{2}} - {4.896\quad s} + 1.615} )}{( {s^{2} + \pi^{2}} )^{2}}$

Note that this filter has a resonant or center frequency of 0.5 Hz butmay be frequency scaled in accordance with known techniques. While thisfilter is known to work appropriately, there are various otherappropriate filter transfer functions.

When the radio frequency power amplifier uses frequency translation anddown converts the output signal to a base band frequency correspondingto an input signal centered at DC a low pass filter will normally beused. This may be comprised of single integrator stages, one for a real(I) path and one for an imaginary (Q) path. Higher order filters mayalso be used, such as the filter depicted in FIG. 21. Recalling thediscussion of FIG. 4, the loop filter needs to filter a complex signaland thus includes a real path 2101 and an imaginary path 2103. Here thesingle integrators noted above are replaced by a second order functionusing, for example, two integrators 2105, 2107 or 2109, 2111 plus asummer 2113 or 2115. Each of the I and Q filters has a transfer functionof the form (1.5 sT+1)/(sT)² as depicted. Note that the output of thesecond integrator is applied to a limiter 2117, 2119. This is a meansfor limiting the maximum contribution of the “momentum” term 1/(sT)².This term is one mechanism that may contribute to instability. Clippingthis term does not ordinarily limit the intended operation of the filterwhen, for example, clipping levels are set at 4 standard deviations.Other stabilization techniques may be applied such as clipping otherintegrator outputs or nulling integrator outputs if the overall outputfrom the filter is too large or does not change sign for too manysamples. Note that the output of the summers 2113, 2115 is used to drivethe complex mixer 407 in FIG. 4.

Referring to FIG. 22, an exemplary state machine that represents anotherembodiment of a sequencer that may be employed in FIG. 1 through FIG. 4,etc. will be discussed and described. “Init” 2201 is the start state.From that state, the output switch or switching stage is immediatelyturned “On” 2203. The machine starts in the “On” state so the choke feedinductor that is supplying the output transistor can charge up. Themachine stays in the “On” state in some embodiments for at least someminimum time “onMin” in order to avoid small glitches and thus avoidpossible issues with the life expectancy of the switching stage andvarious drivers. In this embodiment the machine stays in the “On” stateuntil a threshold level of current, e.g. “iTrigger”, is flowing throughthe switch. This makes sure that the pulse in the output signal is goingto go positive rather than negative when the switch opens. Note that thecatch or snub diode in the various embodiments also enforces this. Thestate machine also remains in the “On” state until the loop filteroutput is negative. This is a way of making the next transition bepositive-edge-triggered.

Given that a sufficient number of these preconditions are satisfied, thestate machine waits for the loop filter plus second feedback signal orsystem to say go, i.e., waits for an initiating signal from the loopfilter, etc.,—“filtwt” 2205 (filter wait). If the loop filter withsecond feedback system says “go” (i.e. makes a transition to a positivevalue) while we're still seeing positive switch current (meaning thatthe pulse will go positive if the switching stage is opened), then openthe switching stage, i.e., go to state “Off” 2207. Note that once theswitching stage is turned off actual output power starts to begenerated, i.e. applied to the resonant circuit and thus load. Otherwiseif the switch current goes negative before the filter and secondfeedback system says “go”, go to state “Iwt” 2209 (“current wait”).“Iwt” just waits for the switch current and loop-filter current phase tobe proper and then goes back to waiting on the filter 2205. This meansthat filter output is negative and thus a positive transition isexpected and further means the switch current is positive so when openeda positive pulse is generated.

Given that the state machine is in the “Off” state 2207; if a maximumtime “offMax” is exceeded in this state, go back 2208 to state “On”2203. This was originally proposed as a failsafe operating mode. Thishas been implemented as the one-shot that resets the D flip flop after acertain period of time. Note that when this transition happens, we maybe wasting power when the switch is not being turned on at a safe time(i.e. when drain voltage is zero). Alternatively if the derivative ofdrain or output voltage goes negative, then the voltage of the outputsignal is on the way back down and the machine goes to state “Off2”2211.

In state “Off2”, the drain or output signal voltage is on the way down;and either it will cross zero or it will turn around, i.e., startincreasing (see FIG. 17). If the output signal voltage turns around andstarts going positive, then turn 2212 the switching stage “On” 2203.Note that from an efficiency perspective this may not be a good thing todo, but similar to transition 2208 it is better than letting the outputsignal voltage continue to increase. Alternatively if the output signalvoltage crosses zero, go to state “clamp” 2213, which effectively turnsthe switching stage on. This can be implemented as a catch diode asnoted in one or more embodiments. Stay in the “clamp” state 2213 untilthe switching stage current goes positive, at which point the statemachine goes to state “On” 2203 (transistor switching stage closed) tohold the voltage down. Note that in the above discussed embodiments orcircuit implementations it's fine to have the transistor “On” even whilethe diode is “clamping”.

Referring to FIG. 23, an alternative embodiment of a sequencer 2300 thatprovides a sequencer output at 2301 asynchronously when synchronouslyclocked, e.g., from a fixed clock 2303. The clock 2303 is shown astoggling for example, at 8 times the carrier frequency for an outputsignal from the corresponding radio frequency power amplifier. Thesequencer 2300 may be arranged to generate a plurality of output signalsor sequencer outputs with each one having a different and correspondingtime profile (e.g., starting and ending time for an OFF state). Thesequencer output is used to drive a switching stage 2305, such as theswitching stage in one of FIG. 1 through FIG. 4 or the like.

The fixed clock running at 8 times the carrier frequency is acompromise. Higher rates would be better for power amplifierperformance, and the sequencer would work at a somewhat lower rate,however 8× is a reasonable compromise between the difficulties of highspeeds and the poor performance of coarser sampling. The D flip flop2307, NAND gate 2309 & inverter 2311 are a zero-crossing detector. Theinput 2313 from “filter output” is assumed to be appropriately levelshifted so that an analogue zero corresponds to the trigger point oflogic inputs. The NAND gate is looking for situations where the inputused to be 0 (so Q bar is “1”) but is now “1”. The inverter 2311converts that into a “1”, i.e., positive logic.

The cross-coupled NOR gates 2315 functionally operate as an RSflip-flop. A “1” out of the zero crossing detector (inverter 2311)forces its upper output, i.e. sequencer output at 2301 to “0”, i.e. theOFF state, which results in a) turning OFF the RF switching stage 2305and thus causing a pulse to start and b) starts the one-shot counting.The one-shot 2317 is a binary down counter that can be preloaded, e.g.with 011 (J0, J1). When the RF switch is “ON”, this counter is preloadedto “011”, i.e. 3 counts plus one delay at a rate of 8× carrier, henceone half-cycle of the carrier. During this “switch ON”—state thecarry-out (negative logic, hence inverted) is zero, keeping the RS flipflop 2315 ready to be triggered by the zero-crossing detector. When theRS flip flop 2315 is triggered and the RF switch turns OFF, the counterstarts to count down towards zero. When it reaches zero, the carry-outresets the RS flip flop 2315 and the switch and system return to the“switch-ON” state awaiting another trigger.

Note that advantageously the feedback control system 113 of FIG. 1 maybe implemented in the discrete time domain using digital signalprocessing techniques and appropriate continuous to digital and digitalto continuous conversion processes at the relevant interfaces.

Other embodiments of the sequencer (not depicted) can select from aplurality of sequencer outputs using interpolation. For example bynoting the filter output and possible earlier or intermediate resultsfrom the filter (e.g., prior to last integrator) at a clock time or atsequential clock times (the clock having a frequency similar to thecarrier frequency), an estimate of the filter output in the recent pastand near future can be made and thus one of the plurality of pulses canbe selected, e.g. from a look up table, to provide the OFF state or ONstate with an appropriate time profile, i.e. a starting time and endingtime. The plurality of pulses would be selected such that each variedfrom the other by a few degrees and thus the appropriate resolution overa carrier period required to control the switching stage would beprovided.

Referring to FIG. 24, a flow chart of a method of providing a radiofrequency signal with complex modulation according to one or moreembodiments will be discussed and described. It is noted that the methodof FIG. 24 may be implemented in one or more of the embodimentsdiscussed above or in alternative radio frequency amplifiers withsimilar functionality. Given that many of the inventive concepts andprinciples embodied in the method of FIG. 24 have been discussed anddescribed above with reference to various apparatus, the presentdiscussion will be in the nature of an overview and summary.

The method 2400 is a method of providing a radio frequency signal withcomplex modulation (AM, PM, or AM & PM), e.g. an amplified version of aninput signal with the same modulation, and begins at 2401 with providingan input signal including complex modulation (AM/PM modulation) at baseband (BB), an intermediate frequency (IF) or radio frequency (RF). At2403 as shown, combining the input signal with a first feedback signalat the same frequency is performed. Next the method includes filteringthe combination of the input signal and the feedback signal 2405 toprovide a filtered signal, where the filtering is done with a low passfilter if the combination signal is a base band signal and ordinarilywith a bandpass filter if the signal is centered at an IF or RF(carrier) frequency. As noted earlier if the input signal is at baseband or at IF typically, it and the feedback signal will be in complexform and the combining process and filtering processes will handlecomplex signals.

Next the optional process 2407 can be used to up convert or frequencytranslate the filtered signal when that signal is at BB or IF. Then 2425shows adding a second feedback signal discussed below to the filteredsignal. Then 2409 shows generating, responsive to the filtered signalplus second feedback signal, a quantized signal having an OFF state, ONstate, etc. where the OFF state begins at a variable time, e.g., thatcorresponds to the filtered signal plus second feedback signal. Thus thegenerating the quantized signal can be directly responsive to the secondfeedback signal. Then 2423 shows providing, responsive to the quantizedsignal, a second feedback signal having, e.g. appropriate gains anddelays, and deployed to affect the generating the quantized signal. Forexample, the second feedback signal can as depicted be added to thefiltered signal at 2425 and thus affect or modify the filtered signalwith the resultant signal used to trigger the generating the quantizedsignal. In alternative embodiments the second feedback signal can becoupled at 2427 to the up conversion process and used, e.g., to vary aphase shift of a local oscillator, and thus a phase of the filteredsignal as up converted or frequency translated with the resultant signalused to trigger generating the quantized signal.

The providing the second feedback signal in some embodiments comprisesforming one or more delayed and weighted versions of the quantizedsignal and combining the one or more delayed and weighted versions ofthe quantized signal to provide the second feedback signal. The formingand the combining in some embodiments comprises forming and combiningcontinuously and asynchronously at least a portion of the one or moredelayed and weighted versions of the quantized signal. As noted above,the providing the second feedback signal can include providing one ormore second feedback signals using one or more of a discrete timeprocess, a continuous time process, and a process with memory. Invarious embodiments, the second feedback signal is deployed to cause theOFF state to begin either earlier or later with the second feedbacksignal than without the second feedback signal. Furthermore, the secondfeedback signal as deployed can affect the variable time to a greaterextent when the filtered signal (input to ADD process 2425) is smallerthan when the filtered signal is larger. Additionally in someembodiments the generating the quantized signal further comprisesgenerating a quantized signal having an ON state with a duration and thesecond feedback signal is deployed to increase a magnitude of adifference between the duration of the ON state and a referenceduration, e.g., T/2, as noted above.

Controlling a radio frequency switching stage with the quantized signalto provide an output signal to a resonant load occurs at 2411. Then at2412 limiting or clipping an amplitude of the output signal isundertaken and this process can feed a power recovery process 2414. Theoutput signal as amplitude limited or clipped is level adjusted 2413 andoptionally down converted in a base band system 2415 and used to providethe first feedback signal at BB, IF, or RF 2417 to the combining processat 2403. Note that the output signal comprises an amplified version ofthe input signal with the complex modulation, i.e., the radio frequencysignal with the complex modulation. The first feedback signalcorresponds to the output signal as clipped or amplitude limited aslevel adjusted and in some instances frequency converted. The outputsignal is filtered 2419 with typically a band pass filter and thenoutput 2421 to a load (antenna, cable, etc.) as a radio frequency signalwith modulation.

Generating the quantized signal can include generating a quantizedsignal having a second state, where the second state starts at a timenear a voltage minimum for the output signal. The quantized signal canfurther comprise an OFF state having a minimum time duration and an ONstate having a variable time duration.

The limiting an amplitude of the output signal 2412 can include couplingthe output signal to a voltage source through one or more diodes, wherethe voltage source establishes an upper value for the amplitude of theoutput signal. The recovering power 2414 corresponds to the limiting theamplitude of the output signal, in that the power recovered is the powerincluded in the higher level pulses. The recovering power further caninclude regulating a voltage using a DC to DC converter having an inputcoupled to the voltage and an output configured to provide a portion ofDC power for the radio frequency switching stage, where the voltage thatis regulated corresponds to an upper value for the amplitude of theoutput signal (see discussion referring to FIG. 6). The recovering powercan further include enabling the DC to DC converter when the voltagecompared to a reference voltage satisfies a known condition, e.g.,voltage exceeds the reference voltage. Note that the power recoveringcan be disabled or isolated from the destination for the recovered powerwhenever no power is being recovered.

The processes, apparatus, and systems, discussed above, and theinventive principles thereof are intended to and can alleviate problemscaused by prior art radio frequency power amplifiers. Using theseprinciples of defining/providing a radio frequency switching stage witha resonant load and managing or controlling switching times using afeedback control loop or system in addition to a clipper or amplitudelimiting technique and in some embodiments a second feedback system cansimplify faithfully reproducing complex modulation with such switchingstages and also allow for reasonable amplifier efficiencies, size andcosts. Using the above noted principles and concepts allows the use ofless capable switching stages (lower costs) as well as facilitates theuse of alternative switching stages from alternative manufacturers ofsuch devices with limited if any change to the radio frequency poweramplifier. This is expected to reduce “costs” (economic, size, weight,life expectancy, power consumption, etc.) associated with radiofrequency power amplifiers in present and future communication systemsand thus facilitate connectivity for users of such systems.

One of the principles used is to control switching times given theswitching stage, accompanying resonant load, and specifics of a radiofrequency signal with complex modulation, such that on average theswitching occurs at or near a voltage minimum across the switchingstage. Using the amplitude limiting or clipping techniques as abovedescribed is beneficial in protecting switching stages, lowers dynamicrange requirements for some elements, increases output power for a givenlevel of breakdown voltage in the switching devices and with the powerrecovery techniques maintains or improves efficiency, and improvessignal to noise (linearity). The use of the second feedback system andsignal as variously noted above allows for longer loop delays in theradio frequency power amplifier while improving or at least maintainingsatisfactory signal to noise (linearity) and efficiency and additionallyhas provided a surprising improvement in signal to noise and efficiencyeven without loop delay. This dramatically reduces power dissipation inand thus increases efficiency of the resultant radio frequency poweramplifier. Various embodiments of methods, systems, and apparatus foreffecting control of switching stages so as to facilitate and providefor faithful complex modulation of resultant radio frequency poweramplifier output signals in an efficient manner have been discussed anddescribed. It is expected that these embodiments or others in accordancewith the present invention will have application to many communicationnetworks. Using the inventive principles and concepts disclosed hereinadvantageously facilitates communications using linear complexmodulation which will be beneficial to users and providers a like.

This disclosure is intended to explain how to fashion and use variousembodiments in accordance with the invention rather than to limit thetrue, intended, and fair scope and spirit thereof. The foregoingdescription is not intended to be exhaustive or to limit the inventionto the precise form disclosed. Modifications or variations are possiblein light of the above teachings. The embodiment(s) was chosen anddescribed to provide the best illustration of the principles of theinvention and its practical application, and to enable one of ordinaryskill in the art to utilize the invention in various embodiments andwith various modifications as are suited to the particular usecontemplated. All such modifications and variations are within the scopeof the invention as determined by the appended claims, as may be amendedduring the pendency of this application for patent, and all equivalentsthereof, when interpreted in accordance with the breadth to which theyare fairly, legally, and equitably entitled.

1. A radio frequency power amplifier comprising: a feedback controlsystem coupled to a signal corresponding to an input signal and a firstfeedback signal and configured to provide a sequencer output; a radiofrequency switching stage driven by the sequencer output and configuredto provide an output signal to drive a resonant load; and a clippersystem coupled to the output signal and configured to limit an amplitudeof the output signal, the first feedback signal corresponding to theoutput signal as limited.
 2. The radio frequency power amplifier ofclaim 1 wherein the clipper system further comprises one or more diodescoupled from the output signal to a reference voltage, the referencevoltage corresponding to a maximum amplitude of the output signal. 3.The radio frequency power amplifier of claim 2 wherein the clippersystem further comprises a voltage source to maintain the referencevoltage.
 4. The radio frequency power amplifier of claim 1 wherein theclipper system further comprises one or more diodes and a power recoverysystem, the one or more diodes coupled from the output signal to thepower recovery system.
 5. The radio frequency power amplifier of claim 4wherein the power recovery system further comprises a DC to DC convertercoupled to the one or more diodes and configured to provide outputpower.
 6. The radio frequency power amplifier of claim 5 wherein thepower recovery system further comprises enabling circuitry configured toenable the DC to DC converter when an input voltage compared to areference voltage satisfies a known condition, the reference voltagecorresponding to a maximum amplitude of the output signal.
 7. The radiofrequency amplifier of claim 4 wherein the DC to DC converter isconfigured to provide an output current when enabled.
 8. The radiofrequency power amplifier of claim 1 wherein the feedback control systemfurther comprises a loop filter with a filter output coupled to an inputof a sequencer, the sequencer configured to provide the sequenceroutput, where the sequencer output has an OFF state with a starting timethat corresponds to the filter output and has a minimum duration and anON state that has a starting time corresponding to a voltage minimum forthe output signal.
 9. The radio frequency power amplifier of claim 1further comprising a second feedback system responsive to the sequenceroutput and configured to provide a second feedback signal that iscoupled to the feedback control system; where the sequencer output hasat least one state with a starting time that is determined by thefeedback control system.
 10. The radio frequency power amplifier ofclaim 9 wherein the feedback control system comprises a sequencerconfigured to provide the sequencer output and the second feedbacksignal is coupled to an input of the sequencer.
 11. The radio frequencypower amplifier of claim 9 wherein the second feedback system comprisesone or more delay stages with outputs coupled to a corresponding one ormore gain stages with each of the gain stages having an output, wherethe second feedback signal corresponds to a combination of the signal atthe output of each of the one or more gain stages.
 12. The radiofrequency power amplifier of claim 1 wherein the radio frequencyswitching stage further comprises a radio frequency switching stageconfigured to switch ON responsive to the sequencer output so that overa multitude of switch ON events an average voltage imposed on the radiofrequency switching stage at the switch ON event is less than ½ of aspecified breakdown voltage associated with the radio frequencyswitching stage.
 13. A radio frequency power amplifier arranged andconfigured to drive a resonant load comprising: a radio frequencyswitching stage with an output that is coupled to a resonant circuit andconfigured to provide an output signal with amplitude modulationcorresponding to amplitude modulation of an input signal when poweredfrom a fixed voltage power supply; a feedback control system coupled tothe input signal and the output signal, the feedback control systemcomprising a sequencer configured to provide a sequencer output that isused to drive the radio frequency switching stage; and an amplitudecontrol system coupled to the output of the radio frequency switchingstage and configured to limit an amplitude of the output signal.
 14. Theradio frequency power amplifier of claim 13 wherein the amplitudecontrol system further comprises one or more diodes coupled from theoutput signal to a load, the load establishing an upper value for theamplitude of the output signal.
 15. The radio frequency power amplifierof claim 14 wherein the load further comprises a voltage sourceproviding a voltage, where the upper value for the amplitude of theoutput signal corresponds to the voltage.
 16. The radio frequency poweramplifier of claim 13 wherein the amplitude control system furthercomprises one or more diodes and a power recovery system, the one ormore diodes coupled from the output signal to the power recovery system.17. The radio frequency power amplifier of claim 16 wherein the powerrecovery system further comprises a DC to DC converter coupled to theone or more diodes and configured to provide a portion of DC power forthe radio frequency power amplifier.
 18. The radio frequency poweramplifier of claim 17 wherein the power recovery system furthercomprises enabling circuitry configured to enable the DC to DC converterwhen an input voltage compared to a reference voltage satisfies a knowncondition, the reference voltage corresponding to an upper value for theamplitude of the output signal.
 19. The radio frequency power amplifierof claim 18 wherein the power recovery system further comprises anelectronic switch to isolate the power recovery system from a DC powersource when the power recovery system is not providing the portion ofthe DC power for the radio frequency power amplifier.
 20. The radiofrequency power amplifier of claim 16 wherein the power recovery systemcomprises a DC to DC converter that is configured to regulate a voltageat an input to the DC to DC converter.
 21. The radio frequency poweramplifier of claim 20 wherein the power recovery system furthercomprises enabling circuitry configured to enable the DC to DC converterwhen a comparison of the voltage and a reference voltage satisfies aknown condition.
 22. The radio frequency power amplifier of claim 13wherein the feedback control system further comprises a loop filter witha filter output coupled to an input of the sequencer, where thesequencer output has an OFF state with a starting time that correspondsto the filter output and has a minimum duration and an ON state that hasa starting time corresponding to a voltage minimum for the outputsignal.
 23. The radio frequency power amplifier of claim 13 furthercomprising a second feedback system responsive to the sequencer outputand configured to provide a second feedback signal that is coupled to aninput of the sequencer; where the sequencer output has at least onestate with a starting time that is determined by the feedback controlsystem and the second feedback system.
 24. The radio frequency poweramplifier of claim 13 wherein the radio frequency switching stage asdriven by the sequencer output is further configured to provide anoutput signal that includes an amplified replica of the input signalover an input signal bandwidth, where the input signal includes complexmodulation while the radio frequency switching stage is powered from aconstant voltage power supply.
 25. The radio frequency power amplifierof claim 13 wherein the feedback control system further comprises amixer arrangement configured to: provide a feedback signal, the feedbacksignal further corresponding to the output signal as down converted bythe mixer arrangement; and provide a sequencer input corresponding to acombination of the input signal and the feedback signal as up convertedby the mixer arrangement.
 26. A method of providing a radio frequencysignal with complex modulation comprising: filtering a combination of aninput signal and a first feedback signal to provide a filtered signal,the input signal including complex modulation; generating, responsive tothe filtered signal, a quantized signal having an OFF state that beginsat a variable time; controlling a radio frequency switching stage withthe quantized signal to provide an output signal to a resonant load; andlimiting an amplitude of the output signal, the output signal as limitedcorresponding to the first feedback signal and further comprising anamplified version of the input signal with the complex modulation. 27.The method of claim 26 wherein the limiting an amplitude of the outputsignal further comprises coupling the output signal to a voltage sourcethrough one or more diodes, the voltage source establishing an uppervalue for the amplitude of the output signal.
 28. The method of claim 26further comprising recovering power corresponding to the limiting anamplitude of the output signal.
 29. The method of claim 28 wherein therecovering power further comprises regulating a voltage using a DC to DCconverter having an input coupled to the voltage and an outputconfigured to provide a portion of DC power for the radio frequencyswitching stage, the voltage corresponding to an upper value for theamplitude of the output signal.
 30. The method of claim 29 wherein therecovering power further comprises enabling the DC to DC converter whenthe voltage compared to a reference voltage satisfies a known condition.